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Simulators
CPU and FDE: SL / HL · Pipelining: HL
Write a little program, assemble it into memory, then step through the fetch-decode-execute cycle and watch each register and bus do its job. Read the theory
Assembly code
An operand can be a number or a label such as x. A label can mark any line, including a DAT line. The assembler replaces each label used as an operand with its address.
Input
Load a program first. A program reads input with the INP instruction.
Output
RAM
Keys: Space play or pause, → step, R reset
Program ready.
The PC holds the address of the next instruction to fetch. It increases by 1 during the fetch. When a branch is taken, the PC is set to the target address.
No write to this register appears in the saved steps.
These two activities show how cache memory and multiple cores help the CPU. They are separate from your assembly program above and do not change it. The cache activity follows one read at a time, and the core activity uses tasks that do not depend on each other.
Choose an address to read its value. The CPU checks L1 first, then checks the next level only after a miss. A hit supplies the value without reading RAM.
L1
Not checked2 entries · lookup +1 unit
L2
Not checked4 entries · lookup +3 units
L3
Not checked6 entries · lookup +8 units
RAM
Not read8 locations · lookup +30 units
All caches are empty. Read an address, then read it again to compare the cost.
Each cache entry holds one value and its address. Any address can use any entry (fully associative). A full cache replaces its least recently used entry. A read moves the entry to the front of each checked cache and copies it into any that missed. Unchecked caches keep their order.
In this example, anything in L1 is also in L2, and anything in L2 is also in L3. When a larger cache removes an entry, any copy of it in the smaller caches is removed too. Real processors use different cache sizes and rules, and some cache levels are shared between cores.
Each checked level adds its cost to the total. These comparison units represent lookup costs only. Cache refill time is excluded. The activity shows one read at a time, with one value per cache entry. It does not model memory writes.
Registers hold the CPU's working values. RAM holds programs and data currently in use and is volatile (its contents are lost without power). ROM is non-volatile (it retains its contents without power) and usually holds firmware. ROM is separate from the cache levels.
Both machines square the same six inputs: 2, 3, 4, 5, 6, 7. Each task takes two work units on one core and uses no other task's result. At every step, each core advances its own task by one unit.
One core
0/6 tasks completeCore 1
Ready
0 work units elapsed.
Two cores
0/6 tasks completeCore 1
Ready
Core 2
Ready
0 work units elapsed.
Step 0: the one-core machine has completed 0 tasks and the two-core machine has completed 0.
The tasks here are independent and equally sized. Both cores work at the same speed, so two cores finish in half the steps. Sharing work and transferring data can take time in real systems. Uneven tasks or dependencies can reduce the benefit. Work units measure this activity only. Pipelining overlaps instruction stages within a core. Each core can have its own pipeline.
A GPU (Graphics Processing Unit) has many processing units that can perform similar operations on many data items at once, such as pixels or matrix elements. A CPU handles a wide range of tasks and can send suitable work to the GPU. Moving data and coordinating the work take time, so using a GPU does not always make a program faster.
A1.1.6 HL, pipelining
Without pipelining, each instruction finishes before the next starts. Pipelining overlaps the stages of several instructions. Both machines below run the same five instructions, with one clock cycle per stage. The counter above counts completed instructions, including HLT. The counters below count clock cycles.
Predict how many clock cycles the pipelined machine needs to run five instructions through four stages.
One instruction at a time
waiting for the clock
Pipelined
waiting for the clock