The CPU: write a program, watch the hardware run it
Write a little program, assemble it into memory, then step through the fetch-decode-execute cycle and watch each register and bus do its job. Read the theory
Assembly code
Instruction set
INP
read the next input value into the accumulator
OUT
send the accumulator to output
LDA x
load the value at address x into the accumulator
STA x
store the accumulator at address x
ADD x
add the value at address x to the accumulator
SUB x
subtract the value at address x from the accumulator
BRA x
branch: jump to address x always
BRZ x
branch to x if the accumulator is zero
BRP x
branch to x if the accumulator is zero or positive
HLT
stop the program
x DAT n
a data cell labelled x, holding the number n
An operand like x is a label you define with DAT; the assembler turns labels into addresses.
Input
Load a program first. INP is what reads input.
Output
nothing yet
fetchdecodeexecutecycle 0
3RAM
AddrData
empty — assemble a program
CPU
A1.1.6 HL, pipelining
Four stages, one clock
One instruction at a time leaves parts of the CPU waiting while another stage works. A pipeline starts the next instruction before the last one finishes, so the units stay busy. Same five instructions, same clock, two machines.
Prediction: five instructions, four stages. Pipelined, how many cycles?